HDL Lab

Profile and objectives

The HDL Lab teaches both theory and practice for the design of highly integrated digital systems with Hardware Description Languages (HDL). In particular, students acquire the hardware description language VHDL.  

Theory teaching contents:

  • Introduction to VHDL-based development
  • Basics of modeling with VHDL
  • Structural versus behavioral modeling
  • Concurrent versus sequential statements
  • Design levels in VHDL
  • Synthesis-compatible modeling
  • Design rules for VHDL
  • Modeling of memories with VHDL
  • Simulation of VHDL models with test benches

Practice teaching contents (project oriented):

In the seminar “Design of highly integrated systems with hardware description languages” in the Bachelor’s degree program Electrical Engineering/Information Technology, students design, simulate, implement and test a complete, complex FPGA project (stopwatch, short time alarm clock, or similar), with an emphasis placed on industry-oriented approaches. Computer-aided development tools that are frequently used in industry (Intel Quartus platform and Mentor ModelSim) are used here as well. For the implementation, high-quality development boards by terasic with Intel Cyclone FPGAs IV or V are available.